Characterization of fabrication process noises for 32nm NMOS devices
This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is...
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| 主要な著者: | , , , |
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2017
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| オンライン･アクセス: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5248 |
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