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Characterization of fabrication process noises for 32nm NMOS devices

This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is...

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主要な著者: Elgomati, H.A., Majlis, B.Y., Ahmad, I., Ziad, T.
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出版事項: 2017
オンライン･アクセス:http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5248
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spelling my.uniten.dspace-52482017-11-15T02:57:02Z Characterization of fabrication process noises for 32nm NMOS devices Elgomati, H.A. Majlis, B.Y. Ahmad, I. Ziad, T. This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is ±1°C variation in sacrificial oxide layer growth by diffusion temperature and also silicide compress annealing temperature. In this project, a working 32 NMOS transistor fabrication is used. By increasing the sacrificial oxide layer diffusion temperature from 900°C to 901°C, the reference 32nm NMOS transistor threshold voltage (VTH) jumps from 0.1181V to 0.1394V, while leakage current drops from 0.111mA/um to 0.109 mA/um. By decreasing the silicide compress temperature from 910°C to 909°C, threshold voltage increase slightly from 0.118053V to 0.118068V, This shows a very different in magnitude of effect from same degree of noise introduce to the fabrication process. © 2010 IEEE. 2017-11-15T02:57:01Z 2017-11-15T02:57:01Z 2010 http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5248
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
description This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is ±1°C variation in sacrificial oxide layer growth by diffusion temperature and also silicide compress annealing temperature. In this project, a working 32 NMOS transistor fabrication is used. By increasing the sacrificial oxide layer diffusion temperature from 900°C to 901°C, the reference 32nm NMOS transistor threshold voltage (VTH) jumps from 0.1181V to 0.1394V, while leakage current drops from 0.111mA/um to 0.109 mA/um. By decreasing the silicide compress temperature from 910°C to 909°C, threshold voltage increase slightly from 0.118053V to 0.118068V, This shows a very different in magnitude of effect from same degree of noise introduce to the fabrication process. © 2010 IEEE.
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author Elgomati, H.A.
Majlis, B.Y.
Ahmad, I.
Ziad, T.
spellingShingle Elgomati, H.A.
Majlis, B.Y.
Ahmad, I.
Ziad, T.
Characterization of fabrication process noises for 32nm NMOS devices
author_facet Elgomati, H.A.
Majlis, B.Y.
Ahmad, I.
Ziad, T.
author_sort Elgomati, H.A.
title Characterization of fabrication process noises for 32nm NMOS devices
title_short Characterization of fabrication process noises for 32nm NMOS devices
title_full Characterization of fabrication process noises for 32nm NMOS devices
title_fullStr Characterization of fabrication process noises for 32nm NMOS devices
title_full_unstemmed Characterization of fabrication process noises for 32nm NMOS devices
title_sort characterization of fabrication process noises for 32nm nmos devices
publishDate 2017
url http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5248
_version_ 1644493627546664960
score 13.251813

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