Characterization of fabrication process noises for 32nm NMOS devices
This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | |
| Published: |
2017
|
| Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5248 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Be the first to leave a comment!