Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method
This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilic...
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| Main Authors: | , , |
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2017
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| Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5222 |
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