Cover Image

Analysis & design low power multiplier using TSMC 0.18µm CMOS technology

As the advance of VLSI technology, low power design has become an important topic in VLSI design. This project is to design a low power multiplier implemented in mentor graphic tools. Low power multipliers are developed through minimizing switching activities of partial product using the radix 4...

Full description

Saved in:
Bibliographic Details
Main Author: Norsaifulrudin Mat Zuki
Other Authors: Nazuhusna Khalid (Advisor)
Format: Learning Object
Language:English
Published: Universiti Malaysia Perlis 2008
Subjects:
Multipliers
Metal oxide semiconductors, Complementary
Integrated circuits > Very large scale integration
Integrated circuits
Low power multipliers
Online Access:http://dspace.unimap.edu.my/xmlui/handle/123456789/1974
Tags: Add Tag
No Tags, Be the first to tag this record!
id my.unimap-1974
record_format dspace
spelling my.unimap-19742008-10-29T04:49:40Z Analysis & design low power multiplier using TSMC 0.18µm CMOS technology Norsaifulrudin Mat Zuki Nazuhusna Khalid (Advisor) Multipliers Metal oxide semiconductors, Complementary Integrated circuits -- Very large scale integration Integrated circuits Low power multipliers As the advance of VLSI technology, low power design has become an important topic in VLSI design. This project is to design a low power multiplier implemented in mentor graphic tools. Low power multipliers are developed through minimizing switching activities of partial product using the radix 4 booth algorithm. Before computation for two input data, the one with a smaller effective dynamic range is processed to generate booth codes, thereby increasing the probability that the partial products become zero. By employing the dynamic-range determination unit to control input data paths, the multiplier with a column-based adder tree of compressors or counters is designed. The proposed 16x16-bit multiplier reduces power consumed by the conventional multiplier. The proposed multiplier design will try to reduce the total power consumption by 20% - 30% when compared with other multiplier. The multipliers proposed herein can be broadly used in various media processing to yield low-power consumption at limited hardware cost. 2008-09-07T03:29:48Z 2008-09-07T03:29:48Z 2008-04 Learning Object http://hdl.handle.net/123456789/1974 en Universiti Malaysia Perlis School of Microelectronic Engineering
institution Universiti Malaysia Perlis
building UniMAP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Perlis
content_source UniMAP Library Digital Repository
url_provider http://dspace.unimap.edu.my/
language English
topic Multipliers
Metal oxide semiconductors, Complementary
Integrated circuits -- Very large scale integration
Integrated circuits
Low power multipliers
spellingShingle Multipliers
Metal oxide semiconductors, Complementary
Integrated circuits -- Very large scale integration
Integrated circuits
Low power multipliers
Norsaifulrudin Mat Zuki
Analysis & design low power multiplier using TSMC 0.18µm CMOS technology
description As the advance of VLSI technology, low power design has become an important topic in VLSI design. This project is to design a low power multiplier implemented in mentor graphic tools. Low power multipliers are developed through minimizing switching activities of partial product using the radix 4 booth algorithm. Before computation for two input data, the one with a smaller effective dynamic range is processed to generate booth codes, thereby increasing the probability that the partial products become zero. By employing the dynamic-range determination unit to control input data paths, the multiplier with a column-based adder tree of compressors or counters is designed. The proposed 16x16-bit multiplier reduces power consumed by the conventional multiplier. The proposed multiplier design will try to reduce the total power consumption by 20% - 30% when compared with other multiplier. The multipliers proposed herein can be broadly used in various media processing to yield low-power consumption at limited hardware cost.
author2 Nazuhusna Khalid (Advisor)
author_facet Nazuhusna Khalid (Advisor)
Norsaifulrudin Mat Zuki
format Learning Object
author Norsaifulrudin Mat Zuki
author_sort Norsaifulrudin Mat Zuki
title Analysis & design low power multiplier using TSMC 0.18µm CMOS technology
title_short Analysis & design low power multiplier using TSMC 0.18µm CMOS technology
title_full Analysis & design low power multiplier using TSMC 0.18µm CMOS technology
title_fullStr Analysis & design low power multiplier using TSMC 0.18µm CMOS technology
title_full_unstemmed Analysis & design low power multiplier using TSMC 0.18µm CMOS technology
title_sort analysis & design low power multiplier using tsmc 0.18µm cmos technology
publisher Universiti Malaysia Perlis
publishDate 2008
url http://dspace.unimap.edu.my/xmlui/handle/123456789/1974
_version_ 1643787510028959744
score 13.22586

Similar Items