8-bits X 8-bits modified Booth 1’s complement multiplier
With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier, thus making them suitable for various high speed...
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| フォーマット: | Learning Object |
| 言語: | English |
| 出版事項: |
Universiti Malaysia Perlis
2008
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| オンライン･アクセス: | http://dspace.unimap.edu.my/xmlui/handle/123456789/1934 |
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