20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY
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2008
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my.utp.eprints.35302017-01-19T08:26:24Z 20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY Assaad, Maher TK Electrical engineering. Electronics Nuclear engineering 2008 Conference or Workshop Item PeerReviewed application/pdf http://eprints.utp.edu.my/3530/1/Binder2.pdf Assaad, Maher (2008) 20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY. In: Proceedings of the 15th International Conference MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. http://eprints.utp.edu.my/3530/ |
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TK Electrical engineering. Electronics Nuclear engineering Assaad, Maher 20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY |
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Conference or Workshop Item |
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Assaad, Maher |
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Assaad, Maher |
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Assaad, Maher |
title |
20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK
DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY |
title_short |
20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK
DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY |
title_full |
20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK
DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY |
title_fullStr |
20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK
DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY |
title_full_unstemmed |
20 GB/S REFERENCELESS QUARTER-RATE PLL-BASED CLOCK
DATA RECOVERY CIRCUIT IN 130 NM CMOS TECHNOLOGY |
title_sort |
20 gb/s referenceless quarter-rate pll-based clock
data recovery circuit in 130 nm cmos technology |
publishDate |
2008 |
url |
http://eprints.utp.edu.my/3530/1/Binder2.pdf http://eprints.utp.edu.my/3530/ |
_version_ |
1738655271461322752 |
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13.211869 |