Low power 130 nm CMOS Johnson Counter with clock gating technique
In a very large scale integration (VLSI) of integrated circuit (IC) nowadays, digital circuit with low power design is the target of the IC designer. This is to prolong the battery life of the circuit especially if it is meant for wearable devices. In most of the digital circuits, counters are used...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IOP Publishing
2018
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/2902/1/AJ%202019%20%2865%29.pdf http://eprints.uthm.edu.my/2902/ https://iopscience.iop.org/article/10.1088/1742-6596/1049/1/012073 |
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