Review of Single Cycle Shifter for Structured LDPC Encoder
Shifter has been used in encoder of structured low density parity check (LDPC) codes due to the nature of its structure. Single clock cycle time of shifter is selected for doing matrix-vector multiplication of LDPC encoding to minimize encoding latency. Among the shifters which complete the mu...
Saved in:
Main Authors: | Anggraeni, Silvia, Hussin, Fawnizu Azmadi, Hamid, Nor Hisham |
---|---|
Format: | Article |
Published: |
Trans Tech Publications Inc.
2015
|
Online Access: | http://eprints.utp.edu.my/11938/1/AMM.763.189.pdf http://eprints.utp.edu.my/11938/ |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
High rate (3, k) regular LDPC encoder architecture
by: Anggraeni, Silvia, et al.
Published: (2011) -
High Throughput Architecture for Low Density Parity Check (LDPC) Encoder
by: Anggraeni, Silvia, et al.
Published: (2013) -
Optimized Encoder Architecture for Structured Low Density Parity Check Codes of Short Length
by: Anggraeni, Silvia, et al.
Published: (2014) -
High throughput architecture for low density parity check (LDPC) encoder
by: Anggraeni, S., et al.
Published: (2013) -
High throughput architecture for low density parity check (LDPC) encoder
by: Anggraeni, S., et al.
Published: (2013)