High throughput architecture for low density parity check (LDPC) encoder
This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed archit...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2013
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| Online Access: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84893175011&doi=10.1109%2fMWSCAS.2013.6674807&partnerID=40&md5=f7572e89e63b24d3968cc90517b9a2a3 http://eprints.utp.edu.my/32594/ |
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