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Review of Single Cycle Shifter for Structured LDPC Encoder

Shifter has been used in encoder of structured low density parity check (LDPC) codes due to the nature of its structure. Single clock cycle time of shifter is selected for doing matrix-vector multiplication of LDPC encoding to minimize encoding latency. Among the shifters which complete the mu...

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Main Authors: Anggraeni, Silvia, Hussin, Fawnizu Azmadi, Hamid, Nor Hisham
Format: Article
Published: Trans Tech Publications Inc. 2015
Online Access:http://eprints.utp.edu.my/11938/1/AMM.763.189.pdf
http://eprints.utp.edu.my/11938/
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spelling my.utp.eprints.119382017-01-19T08:20:57Z Review of Single Cycle Shifter for Structured LDPC Encoder Anggraeni, Silvia Hussin, Fawnizu Azmadi Hamid, Nor Hisham Shifter has been used in encoder of structured low density parity check (LDPC) codes due to the nature of its structure. Single clock cycle time of shifter is selected for doing matrix-vector multiplication of LDPC encoding to minimize encoding latency. Among the shifters which complete the multiplication within one clock cycle, this paper suggests the cyclic shifter for structured LDPC encoder. It is shown that the implementation of the typical cyclic shifter has less logic gates and less bit controller than the other shifter. Trans Tech Publications Inc. 2015 Article PeerReviewed application/pdf http://eprints.utp.edu.my/11938/1/AMM.763.189.pdf Anggraeni, Silvia and Hussin, Fawnizu Azmadi and Hamid, Nor Hisham (2015) Review of Single Cycle Shifter for Structured LDPC Encoder. Applied Mechanics and Materials, 763 . ISSN 1660-9336 http://eprints.utp.edu.my/11938/
institution Universiti Teknologi Petronas
building UTP Resource Centre
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Petronas
content_source UTP Institutional Repository
url_provider http://eprints.utp.edu.my/
description Shifter has been used in encoder of structured low density parity check (LDPC) codes due to the nature of its structure. Single clock cycle time of shifter is selected for doing matrix-vector multiplication of LDPC encoding to minimize encoding latency. Among the shifters which complete the multiplication within one clock cycle, this paper suggests the cyclic shifter for structured LDPC encoder. It is shown that the implementation of the typical cyclic shifter has less logic gates and less bit controller than the other shifter.
format Article
author Anggraeni, Silvia
Hussin, Fawnizu Azmadi
Hamid, Nor Hisham
spellingShingle Anggraeni, Silvia
Hussin, Fawnizu Azmadi
Hamid, Nor Hisham
Review of Single Cycle Shifter for Structured LDPC Encoder
author_facet Anggraeni, Silvia
Hussin, Fawnizu Azmadi
Hamid, Nor Hisham
author_sort Anggraeni, Silvia
title Review of Single Cycle Shifter for Structured LDPC Encoder
title_short Review of Single Cycle Shifter for Structured LDPC Encoder
title_full Review of Single Cycle Shifter for Structured LDPC Encoder
title_fullStr Review of Single Cycle Shifter for Structured LDPC Encoder
title_full_unstemmed Review of Single Cycle Shifter for Structured LDPC Encoder
title_sort review of single cycle shifter for structured ldpc encoder
publisher Trans Tech Publications Inc.
publishDate 2015
url http://eprints.utp.edu.my/11938/1/AMM.763.189.pdf
http://eprints.utp.edu.my/11938/
_version_ 1738655991046602752
score 13.211869

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