Pipelined architecture for low density parity check encoder
This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two meth...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2012
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| Subjects: | |
| Online Access: | http://eprints.utp.edu.my/8826/1/06306129.pdf http://dx.doi.org/10.1109/ICIAS.2012.6306129 http://eprints.utp.edu.my/8826/ |
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