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A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process

This study investigated the use of a built-in-self-test (BIST) module detecting catastrophic errors in photon-counter accumulator for liquid contamination level measurement. Efficient algorithms are exceptionally demanded for a high-count rate and low voltage system photon counting circuit on-chip....

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主要な著者: S., Isaak, H. C., Yeo, C. K., Chang, Y., Yusuf
フォーマット: Conference or Workshop Item
言語:English
出版事項: 2022
主題:
TK Electrical engineering. Electronics Nuclear engineering
オンライン･アクセス:http://eprints.utm.my/id/eprint/98859/1/SIsaac2022_ABuiltInSelfTestModule.pdf
http://eprints.utm.my/id/eprint/98859/
http://dx.doi.org/10.1088/1742-6596/2312/1/012039
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id my.utm.98859
record_format eprints
spelling my.utm.988592023-02-02T09:51:32Z http://eprints.utm.my/id/eprint/98859/ A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process S., Isaak H. C., Yeo C. K., Chang Y., Yusuf TK Electrical engineering. Electronics Nuclear engineering This study investigated the use of a built-in-self-test (BIST) module detecting catastrophic errors in photon-counter accumulator for liquid contamination level measurement. Efficient algorithms are exceptionally demanded for a high-count rate and low voltage system photon counting circuit on-chip. The photon counter sensors are also required high sensitivity digital counter that encodes the arrival of photon in precise timing to prevent any count erroring the absence of light. The proposed BIST is integrated on the data acquisition system, where the accumulator is located. The design circuit, functionality and topology tests of BIST and circuit under test are realized with 180 nm Silterra CMOS Process. The same Verilog codes are verified using field programmable gate array (FPGA) to predict the hardware functionality prior fabrication. The measurement was able to detect at least 90 % fault coverage within 16-bit data acquisition system at minimum operating frequency of 166.7 MHz. 2022 Conference or Workshop Item PeerReviewed application/pdf en http://eprints.utm.my/id/eprint/98859/1/SIsaac2022_ABuiltInSelfTestModule.pdf S., Isaak and H. C., Yeo and C. K., Chang and Y., Yusuf (2022) A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process. In: 3rd International Conference on Emerging Electrical Energy, Electronics and Computing Technologies 2021, ICE4CT 2021, 16 December 2021 - 17 December 2021, Virtual, Online. http://dx.doi.org/10.1088/1742-6596/2312/1/012039
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
S., Isaak
H. C., Yeo
C. K., Chang
Y., Yusuf
A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process
description This study investigated the use of a built-in-self-test (BIST) module detecting catastrophic errors in photon-counter accumulator for liquid contamination level measurement. Efficient algorithms are exceptionally demanded for a high-count rate and low voltage system photon counting circuit on-chip. The photon counter sensors are also required high sensitivity digital counter that encodes the arrival of photon in precise timing to prevent any count erroring the absence of light. The proposed BIST is integrated on the data acquisition system, where the accumulator is located. The design circuit, functionality and topology tests of BIST and circuit under test are realized with 180 nm Silterra CMOS Process. The same Verilog codes are verified using field programmable gate array (FPGA) to predict the hardware functionality prior fabrication. The measurement was able to detect at least 90 % fault coverage within 16-bit data acquisition system at minimum operating frequency of 166.7 MHz.
format Conference or Workshop Item
author S., Isaak
H. C., Yeo
C. K., Chang
Y., Yusuf
author_facet S., Isaak
H. C., Yeo
C. K., Chang
Y., Yusuf
author_sort S., Isaak
title A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process
title_short A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process
title_full A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process
title_fullStr A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process
title_full_unstemmed A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process
title_sort built-in self-test module for 16-bit parallel photon counting circuit using 180 nm cmos process
publishDate 2022
url http://eprints.utm.my/id/eprint/98859/1/SIsaac2022_ABuiltInSelfTestModule.pdf
http://eprints.utm.my/id/eprint/98859/
http://dx.doi.org/10.1088/1742-6596/2312/1/012039
_version_ 1758578029407240192
score 13.251813

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