A 2 Kbit memory array of mixed-VT GC-eDRAM implemented in 130nm standard CMOS technology
The minimization of very large-scale integrated circuits is facing a great challenge as the demands of devices with low power, and high-performance characteristics have intensely increased. Achieving a downscaled embedded memory design with a low leakage power, high stability, and minimized area bec...
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| Main Authors: | , , , , , |
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| Format: | Conference or Workshop Item |
| Published: |
2021
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/98151/ http://dx.doi.org/10.1109/RSM52397.2021.9511591 |
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