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Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias

The reported failure of the Cu-filled via adjacent to the SiO2 liner of a TSV interconnect under thermal-mechanical stressing calls for a thorough quantitative investigation. In this respect, this paper presents a FE-based methodology to quantify the mechanics of deformation and failure processes of...

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Main Authors: Afripin, M. A. A., Yoon, C. K., Tamin, Mohd. Nasir
Format: Conference or Workshop Item
Published: 2018
Subjects:
TJ Mechanical engineering and machinery
Online Access:http://eprints.utm.my/id/eprint/81882/
http://dx.doi.org/10.1109/IMPACT.2017.8255912
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spelling my.utm.818822019-09-30T12:59:36Z http://eprints.utm.my/id/eprint/81882/ Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias Afripin, M. A. A. Yoon, C. K. Tamin, Mohd. Nasir TJ Mechanical engineering and machinery The reported failure of the Cu-filled via adjacent to the SiO2 liner of a TSV interconnect under thermal-mechanical stressing calls for a thorough quantitative investigation. In this respect, this paper presents a FE-based methodology to quantify the mechanics of deformation and failure processes of the Cu-filled via. The simulation employs Johnson-Cook constitutive model and damage equation to represent the damage response of the TSV interconnect to the temperature changes (ζ1Γ=-125 °C; 5, 15 and 45 °C/min). Results show that the large shear stress and stress gradient in the Cu-filled via adjacent to the SiO2 liner is detrimental to crack initiation. A staggered TSV array with pitch length-to-via diameter of 2 is unable to accommodate any transistor without adversely affecting its performance. 2018-01-12 Conference or Workshop Item PeerReviewed Afripin, M. A. A. and Yoon, C. K. and Tamin, Mohd. Nasir (2018) Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias. In: 12th International Microsystems, Packaging, Assembly and Circuits Technology Conference, IMPACT 2017, 25 October 2017 through 27 October 2017, Taipei Nangang Exhibition Center Taipei, Taiwan. http://dx.doi.org/10.1109/IMPACT.2017.8255912
institution Universiti Teknologi Malaysia
building UTM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Teknologi Malaysia
content_source UTM Institutional Repository
url_provider http://eprints.utm.my/
topic TJ Mechanical engineering and machinery
spellingShingle TJ Mechanical engineering and machinery
Afripin, M. A. A.
Yoon, C. K.
Tamin, Mohd. Nasir
Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias
description The reported failure of the Cu-filled via adjacent to the SiO2 liner of a TSV interconnect under thermal-mechanical stressing calls for a thorough quantitative investigation. In this respect, this paper presents a FE-based methodology to quantify the mechanics of deformation and failure processes of the Cu-filled via. The simulation employs Johnson-Cook constitutive model and damage equation to represent the damage response of the TSV interconnect to the temperature changes (ζ1Γ=-125 °C; 5, 15 and 45 °C/min). Results show that the large shear stress and stress gradient in the Cu-filled via adjacent to the SiO2 liner is detrimental to crack initiation. A staggered TSV array with pitch length-to-via diameter of 2 is unable to accommodate any transistor without adversely affecting its performance.
format Conference or Workshop Item
author Afripin, M. A. A.
Yoon, C. K.
Tamin, Mohd. Nasir
author_facet Afripin, M. A. A.
Yoon, C. K.
Tamin, Mohd. Nasir
author_sort Afripin, M. A. A.
title Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias
title_short Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias
title_full Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias
title_fullStr Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias
title_full_unstemmed Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias
title_sort methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias
publishDate 2018
url http://eprints.utm.my/id/eprint/81882/
http://dx.doi.org/10.1109/IMPACT.2017.8255912
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score 13.223943

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