Methodology for thermal-mechanical modeling of damage and failure processes in through-silicon-vias
The reported failure of the Cu-filled via adjacent to the SiO2 liner of a TSV interconnect under thermal-mechanical stressing calls for a thorough quantitative investigation. In this respect, this paper presents a FE-based methodology to quantify the mechanics of deformation and failure processes of...
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| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2018
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/81882/ http://dx.doi.org/10.1109/IMPACT.2017.8255912 |
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| Summary: | The reported failure of the Cu-filled via adjacent to the SiO2 liner of a TSV interconnect under thermal-mechanical stressing calls for a thorough quantitative investigation. In this respect, this paper presents a FE-based methodology to quantify the mechanics of deformation and failure processes of the Cu-filled via. The simulation employs Johnson-Cook constitutive model and damage equation to represent the damage response of the TSV interconnect to the temperature changes (ζ1Γ=-125 °C; 5, 15 and 45 °C/min). Results show that the large shear stress and stress gradient in the Cu-filled via adjacent to the SiO2 liner is detrimental to crack initiation. A staggered TSV array with pitch length-to-via diameter of 2 is unable to accommodate any transistor without adversely affecting its performance. |
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