An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As designdimension shrinks, the interconnect delay becomes the dominant factor for overall signal delay. Buffer insertion is provento be an effective technique to minimize the interconnect delay. In conven...
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| Main Authors: | , |
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| Format: | Article |
| Published: |
Asian Research Publishing Network
2015
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/57782/ http://www.arpnjournals.org/jeas/research_papers/rp_2015/jeas_1015_2794.pdf |
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