An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As designdimension shrinks, the interconnect delay becomes the dominant factor for overall signal delay. Buffer insertion is provento be an effective technique to minimize the interconnect delay. In conven...
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my.utm.577822021-08-15T01:25:43Z http://eprints.utm.my/id/eprint/57782/ An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets Uttraphan, C. Shaikh Husin, N. TK Electrical engineering. Electronics Nuclear engineering In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As designdimension shrinks, the interconnect delay becomes the dominant factor for overall signal delay. Buffer insertion is provento be an effective technique to minimize the interconnect delay. In conventional buffer insertion algorithms, the buffers areinserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertionin their area. Many conventional buffer insertion algorithms do not consider these obstacles. This paper presents analgorithm for simultaneous routing and buffer insertion using look-ahead optimization technique. Simulation results showthat the proposed algorithm can produce up to 47% better solution compared to the conventional algorithms. Althoughresearch has shown that simultaneous routing and buffer insertion is NP-complete, however, with the aid of look-aheadtechnique, the runtime of the algorithm can be reduced significantly. Asian Research Publishing Network 2015 Article PeerReviewed Uttraphan, C. and Shaikh Husin, N. (2015) An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets. ARPN Journal of Engineering and Applied Sciences, 10 (19). pp. 8765-8773. ISSN 1819-6608 http://www.arpnjournals.org/jeas/research_papers/rp_2015/jeas_1015_2794.pdf |
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TK Electrical engineering. Electronics Nuclear engineering Uttraphan, C. Shaikh Husin, N. An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets |
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In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As designdimension shrinks, the interconnect delay becomes the dominant factor for overall signal delay. Buffer insertion is provento be an effective technique to minimize the interconnect delay. In conventional buffer insertion algorithms, the buffers areinserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertionin their area. Many conventional buffer insertion algorithms do not consider these obstacles. This paper presents analgorithm for simultaneous routing and buffer insertion using look-ahead optimization technique. Simulation results showthat the proposed algorithm can produce up to 47% better solution compared to the conventional algorithms. Althoughresearch has shown that simultaneous routing and buffer insertion is NP-complete, however, with the aid of look-aheadtechnique, the runtime of the algorithm can be reduced significantly. |
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Article |
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Uttraphan, C. Shaikh Husin, N. |
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Uttraphan, C. Shaikh Husin, N. |
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Uttraphan, C. |
title |
An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets |
title_short |
An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets |
title_full |
An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets |
title_fullStr |
An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets |
title_full_unstemmed |
An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets |
title_sort |
optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets |
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Asian Research Publishing Network |
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2015 |
url |
http://eprints.utm.my/id/eprint/57782/ http://www.arpnjournals.org/jeas/research_papers/rp_2015/jeas_1015_2794.pdf |
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