An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets
In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As designdimension shrinks, the interconnect delay becomes the dominant factor for overall signal delay. Buffer insertion is provento be an effective technique to minimize the interconnect delay. In conven...
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| Main Authors: | , |
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| Format: | Article |
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Asian Research Publishing Network
2015
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/57782/ http://www.arpnjournals.org/jeas/research_papers/rp_2015/jeas_1015_2794.pdf |
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| Summary: | In today’s VLSI design, one of the most critical performance metric is the interconnect delay. As designdimension shrinks, the interconnect delay becomes the dominant factor for overall signal delay. Buffer insertion is provento be an effective technique to minimize the interconnect delay. In conventional buffer insertion algorithms, the buffers areinserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertionin their area. Many conventional buffer insertion algorithms do not consider these obstacles. This paper presents analgorithm for simultaneous routing and buffer insertion using look-ahead optimization technique. Simulation results showthat the proposed algorithm can produce up to 47% better solution compared to the conventional algorithms. Althoughresearch has shown that simultaneous routing and buffer insertion is NP-complete, however, with the aid of look-aheadtechnique, the runtime of the algorithm can be reduced significantly. |
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