Fault detection with optimum March Test Algorithm

Integrating a large number of embedded memories in System-on-Chips (SoC’s) occupies up to more than 70% of the die size, thus requiring Built-In Self-Test (BIST) with the smallest possible area overhead. This paper analyzes MATS++(6N), March C-(10N), March SR(14N), and March CL(12N) test algori...

全面介绍

Saved in:
书目详细资料
Main Authors: Zakaria, Nor Azura, Wan Hasan, Wan Zuha, Abdul Halin, Izhal, Mohd Sidek, Roslina, Wen, Xiaoqing
格式: Conference or Workshop Item
出版: IEEE 2012
在线阅读:http://psasir.upm.edu.my/id/eprint/40179/
标签: 添加标签
没有标签, 成为第一个标记此记录!
实物特征
总结:Integrating a large number of embedded memories in System-on-Chips (SoC’s) occupies up to more than 70% of the die size, thus requiring Built-In Self-Test (BIST) with the smallest possible area overhead. This paper analyzes MATS++(6N), March C-(10N), March SR(14N), and March CL(12N) test algorithms and shows that they cannot detect either Write Disturb Faults (WDFs) or Deceptive Read Destructive Faults (DRDFs) or both. Therefore to improve fault detection, an automation program is developed based on sequence operation (SQ) generation rules. However after solving the undetected fault, the outcome in term of its detection result of Static Double Cell Faults using the specified test algorithm especially Transition Coupling Faults (CFtrs), Write Destructive Coupling Faults (CFwds), Read Destructive Coupling Faults (CFrds) and Deceptive Read Destructive Faults (CFdrds) are observed.