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Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling

This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as...

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Main Authors: Noor Faizah, Z.A., Ahmad, I., Ker, P.J., Siti Munirah, Y., Mohd Firdaus, R., Md Fazle, E., Menon, P.S.
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Published: 2017
Online Access:http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5185
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spelling my.uniten.dspace-51852017-11-15T02:56:24Z Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling Noor Faizah, Z.A. Ahmad, I. Ker, P.J. Siti Munirah, Y. Mohd Firdaus, R. Md Fazle, E. Menon, P.S. This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively. © 2016 The Authors, published by EDP Sciences. 2017-11-15T02:56:24Z 2017-11-15T02:56:24Z 2016 http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5185
institution Universiti Tenaga Nasional
building UNITEN Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Tenaga Nasional
content_source UNITEN Institutional Repository
url_provider http://dspace.uniten.edu.my/
description This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF) of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively. © 2016 The Authors, published by EDP Sciences.
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author Noor Faizah, Z.A.
Ahmad, I.
Ker, P.J.
Siti Munirah, Y.
Mohd Firdaus, R.
Md Fazle, E.
Menon, P.S.
spellingShingle Noor Faizah, Z.A.
Ahmad, I.
Ker, P.J.
Siti Munirah, Y.
Mohd Firdaus, R.
Md Fazle, E.
Menon, P.S.
Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling
author_facet Noor Faizah, Z.A.
Ahmad, I.
Ker, P.J.
Siti Munirah, Y.
Mohd Firdaus, R.
Md Fazle, E.
Menon, P.S.
author_sort Noor Faizah, Z.A.
title Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling
title_short Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling
title_full Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling
title_fullStr Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling
title_full_unstemmed Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling
title_sort process parameters optimization of 14nm mosfet using 2-d analytical modelling
publishDate 2017
url http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5185
_version_ 1644493608676491264
score 13.211869

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