Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling
This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2) as dielectric and Tungsten Silicide (WSi2) and Titanium Silicide (TiSi2) as...
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| 主要な著者: | , , , , , , |
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| 出版事項: |
2017
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| オンライン･アクセス: | http://dspace.uniten.edu.my/jspui/handle/123456789/5972 |
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