Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor
In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate...
Saved in:
Main Authors: | Afifah Maheran A.H., Menon P.S., Ahmad I., Shaari S., Elgomati H.A., Salehuddin F. |
---|---|
Other Authors: | 36570222300 |
Format: | Conference paper |
Published: |
Institute of Physics Publishing
2023
|
Subjects: | |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Scaling down of the 32 nm to 22 nm gate length NMOS transistor
by: Afifah Maheran A.H., et al.
Published: (2023) -
Comparison between single and multi gates for minimization of warpage using taguchi method in injection molding process for ABS material
by: Mohd. Nasir, Mat Saad, et al.
Published: (2014) -
Modelling of process parameters for 32nm PMOS transistor using Taguchi method
by: Elgomati H.A., et al.
Published: (2023) -
Cobalt silicide and titanium silicide effects on nano devices
by: Elgomati H.A., et al.
Published: (2023) -
Experimental Analysis of the efficiency of tungsten inert gas (TIG) machining for different materials
by: Ong Wei, Koon
Published: (2016)