Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor
In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate...
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2023
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my.uniten.dspace-294612023-12-28T12:13:13Z Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. Elgomati H.A. Salehuddin F. 36570222300 57201289731 12792216600 6603595092 36536722700 36239165300 Metal analysis Nanotechnology Signal to noise ratio Silicides Taguchi methods Threshold voltage Titanium dioxide Analysis of means Design and optimization Experiment design High-k/metal gates Noise parameters Optimum parameters Process parameters Tungsten silicide Analysis of variance (ANOVA) In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V �0.027 for the NMOS device which is in line with projections by the ITRS specifications. Final 2023-12-28T04:13:13Z 2023-12-28T04:13:13Z 2013 Conference paper 10.1088/1742-6596/431/1/012026 2-s2.0-84876950567 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84876950567&doi=10.1088%2f1742-6596%2f431%2f1%2f012026&partnerID=40&md5=315facb720a627ed87e9be4430271e60 https://irepository.uniten.edu.my/handle/123456789/29461 431 1 12026 All Open Access; Bronze Open Access Institute of Physics Publishing Scopus |
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Metal analysis Nanotechnology Signal to noise ratio Silicides Taguchi methods Threshold voltage Titanium dioxide Analysis of means Design and optimization Experiment design High-k/metal gates Noise parameters Optimum parameters Process parameters Tungsten silicide Analysis of variance (ANOVA) |
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Metal analysis Nanotechnology Signal to noise ratio Silicides Taguchi methods Threshold voltage Titanium dioxide Analysis of means Design and optimization Experiment design High-k/metal gates Noise parameters Optimum parameters Process parameters Tungsten silicide Analysis of variance (ANOVA) Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. Elgomati H.A. Salehuddin F. Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor |
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In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSix). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (Vth). The objective of this experiment is to minimize the variance of Vth where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of Vth. The results show that the Vth values have least variance and the mean value can be adjusted to 0.306V �0.027 for the NMOS device which is in line with projections by the ITRS specifications. |
| author2 |
36570222300 |
| author_facet |
36570222300 Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. Elgomati H.A. Salehuddin F. |
| format |
Conference paper |
| author |
Afifah Maheran A.H. Menon P.S. Ahmad I. Shaari S. Elgomati H.A. Salehuddin F. |
| author_sort |
Afifah Maheran A.H. |
| title |
Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor |
| title_short |
Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor |
| title_full |
Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor |
| title_fullStr |
Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor |
| title_full_unstemmed |
Design and optimization of 22 nm gate length high-k/metal gate NMOS transistor |
| title_sort |
design and optimization of 22 nm gate length high-k/metal gate nmos transistor |
| publisher |
Institute of Physics Publishing |
| publishDate |
2023 |
| _version_ |
1806425529314705408 |
| score |
13.222552 |