The analysis of soft error in static random access memory and mitigation by using transmission gate
As the progress of technology continues in accordance to Moore’s law, the density and downsizing of circuitry presents a significant vulnerability to the effects of soft errors. This study proposed a novel method to mitigate soft errors by increasing the robustness of complementary metal oxide semic...
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| Main Authors: | , |
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| 格式: | Article |
| 語言: | English |
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Institute of Advanced Engineering and Science (IAES)
2024
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| 主題: | |
| 在線閱讀: | http://ir.unimas.my/id/eprint/46148/1/7664-22391-1-PB.pdf http://ir.unimas.my/id/eprint/46148/ https://beei.org/index.php/EEI/article/view/7664 https://doi.org/10.11591/eei.v13i6.7664 |
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| 總結: | As the progress of technology continues in accordance to Moore’s law, the density and downsizing of circuitry presents a significant vulnerability to the effects of soft errors. This study proposed a novel method to mitigate soft errors by increasing the robustness of complementary metal oxide semiconductor (CMOS) technology against soft errors via the use of transmission gates within the memory nodes of static random access memory (SRAM) which functioned as a low pass filter that disallowed the occurrence of data corruption. The proposed SRAM was tested against parameter variation of supply voltage and temperature. The critical charge was observed to increase with supply voltage increase, with the opposite being true of the increase in temperature. The increase in critical charge of up to 88.63% was achieved with regards to parameter variation for the transmission gate SRAM in comparison to the 6T SRAM. |
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