A Performance Comparison Study on Multiplier Designs
This study investigates the relative performances of Array, Wallace, Dadda and Reduced Area multipliers for several synthesis optimization modes. All multiplier designs were modeled in Verilog HDL and synthesized based on the TSMC 0.35-micron ASIC Design Kit standard cell library. Performance d...
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| Main Authors: | , , , |
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| 格式: | Article |
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2010
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| 在線閱讀: | http://eprints.utp.edu.my/4988/3/stamp.jsp%3Ftp%3D%26arnumber%3D5716117%26tag%3D1 http://eprints.utp.edu.my/4988/ |
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