False path identification algorithm framework for nonseparable controller-data path circuits
In order to achieve the less test generation complexity, design-for-testability (DFT) techniques are used which causes untestable paths to be testable. These testable path delays have no effect on circuit performance are called false paths. It has been contended that such false paths should not be d...
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| 主要な著者: | , , |
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| フォーマット: | Conference or Workshop Item |
| 出版事項: |
2016
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| オンライン･アクセス: | http://eprints.utp.edu.my/11957/1/1570256625_ICIAS2016.pdf http://eprints.utp.edu.my/11957/ |
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