Effect of low-k oxide thickness variation on gate-all-around floating gate with optimized SiO2/La2O3 tunnel barrier
This paper reports the use of a novel lanthanum oxide (La2O3) tunnel barrier layer with low-k materials, silicon dioxide (SiO2) to improve Gate-All-Around Floating Gate (GAA-FG) memory performance performed using 3-Dimensional (3D) simulator of Silvaco ATLAS. We examine the ability of Variable Oxide...
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| 主要な著者: | , , , , , |
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| フォーマット: | 論文 |
| 出版事項: |
Institute of Physics Publishing
2019
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| 主題: | |
| オンライン･アクセス: | http://eprints.utm.my/id/eprint/88655/ http://dx.doi.org/10.1088/2053-1591/ab2869 |
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| 要約: | This paper reports the use of a novel lanthanum oxide (La2O3) tunnel barrier layer with low-k materials, silicon dioxide (SiO2) to improve Gate-All-Around Floating Gate (GAA-FG) memory performance performed using 3-Dimensional (3D) simulator of Silvaco ATLAS. We examine the ability of Variable Oxide Thickness (VARIOT) concept for several high-k dielectric materials using lanthanum oxide, yttrium (III) oxide, aluminum oxide, zirconium dioxide and hafnium (IV) oxide (La2O3, Y2O3, Al2O3, ZrO2 and HfO2) to evaluate the memory characteristics including tunneling current, program/erase (P/E) operation and memory window. In this work, low-k oxide thickness, SiO2 is varied at 1:1:4 nm. Importantly, this finding shows that the combination of SiO2/La2O3 asymmetric stack have distinct consequences at the lowest programming voltage with Vprog = 4.7 V. In addition, the ability of silicon dioxide / lanthanum oxide (SiO2/La2O3) tunnel stack is significantly improved when the low-k oxide thickness, SiO2 is reduced. The proposed thickness ratio of SiO2 on GAA-FG memory cell yields substantial increased in memory window from 0.04 V to 5.0 V at the same P/E time, t = 0.1 ms. The optimized SiO2/La2O3 combination in this study demonstrated potentials flash memory architecture in the future. |
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