Power-aware through-silicon-via minimization by partitioning finite state machine with datapath
This paper proposes an extended Finite State Machine with Datapath (FSMD) partitioning that performs three-dimensional (3D) high level synthesis (HLS) with objectives to minimize the number of through-silicon-via (TSV) and to equip the synthesized system with power gating capability to save power. T...
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| 主要な著者: | , , , |
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| フォーマット: | Conference or Workshop Item |
| 出版事項: |
Institute of Electrical and Electronics Engineers Inc.
2016
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| 主題: | |
| オンライン･アクセス: | http://eprints.utm.my/id/eprint/73108/ https://www.scopus.com/inward/record.uri?eid=2-s2.0-84983419729&doi=10.1109%2fISCAS.2016.7538954&partnerID=40&md5=33ab547ae1e73ef425675a417f226e92 |
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