s.RABILA2: an optimal VLSI routing algorithm with buffer insertion using iterative RLC model
Buffer insertion and wire sizing have been proven effective in solving the timing optimization problem in VLSI interconnect design. In this paper, we describe a graph-based maze interconnect routing algorithm for VLSI designs. An interconnect routing and buffer insertion with look-ahead algorithm is...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Conference or Workshop Item |
| Published: |
2012
|
| Online Access: | http://eprints.utm.my/id/eprint/34199/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|