Iterative RLC models for interconnect delay optimization in VLSI routing algorithms
Buffer insertion (van Ginneken, 1990), and wire-sizing techniques (Lillis, Cheng and Lin, 1996) have been widely used to minimize global interconnect delay path between interconnect source and sink points. These techniques rely on delay models (Pileggi, 1995) to estimate buffer insertion points – fr...
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| Main Authors: | , , , |
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| Format: | Book Section |
| Language: | English |
| Published: |
Penerbit UTM
2008
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/31035/1/MohamedKhalilHani2008_IterativeRLCModelsforInterconnectDelay.pdf http://eprints.utm.my/id/eprint/31035/ |
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