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Systolic array architecture and its application in finite impulse response filter design

This project presents the methodology involved in mapping a computing algorithm onto Systolic Array (SA) architecture and its implementation in designing a high computational throughput Finite Impulse Response (FIR) filter. As in many applications of Digital Signal Processing (DSP), FIR filtering re...

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Main Author:	Kadir, Ezdiani Idayu
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/33298/5/EzdianiIdayuKadirMFKE2013.pdf http://eprints.utm.my/id/eprint/33298/
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id	my.utm.33298
record_format	eprints
spelling	my.utm.332982017-09-11T08:49:23Z http://eprints.utm.my/id/eprint/33298/ Systolic array architecture and its application in finite impulse response filter design Kadir, Ezdiani Idayu TK Electrical engineering. Electronics Nuclear engineering This project presents the methodology involved in mapping a computing algorithm onto Systolic Array (SA) architecture and its implementation in designing a high computational throughput Finite Impulse Response (FIR) filter. As in many applications of Digital Signal Processing (DSP), FIR filtering requires enormous computing power, especially for applications in real-time environment where fast computations of data is demanded. Fortunately, the FIR filter algorithm is a compute-bound computation, and speeding up this computation can be achieved through systolic approach. Prior to designing the SA FIR filter hardware module in Quartus II, the FIR filter was first designed and analyzed via MATLAB to obtain the filter coefficients and simulation results needed in hardware design. Verification and performance analyses of the SA FIR filter were done based on both simulation results from MATLAB and hardware designs. Simulation result of the SA FIR filter proved the capability of SA architecture to produce high computational throughput, but at the expense of a large number of resources. In addition, the simulation results displayed some limitations of this particular design in terms of its response time and accuracy of the results. Thus, improvements of the design have been proposed to increase its performance. 2013-01 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/id/eprint/33298/5/EzdianiIdayuKadirMFKE2013.pdf Kadir, Ezdiani Idayu (2013) Systolic array architecture and its application in finite impulse response filter design. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering.
institution	Universiti Teknologi Malaysia
building	UTM Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Teknologi Malaysia
content_source	UTM Institutional Repository
url_provider	http://eprints.utm.my/
language	English
topic	TK Electrical engineering. Electronics Nuclear engineering
spellingShingle	TK Electrical engineering. Electronics Nuclear engineering Kadir, Ezdiani Idayu Systolic array architecture and its application in finite impulse response filter design
description	This project presents the methodology involved in mapping a computing algorithm onto Systolic Array (SA) architecture and its implementation in designing a high computational throughput Finite Impulse Response (FIR) filter. As in many applications of Digital Signal Processing (DSP), FIR filtering requires enormous computing power, especially for applications in real-time environment where fast computations of data is demanded. Fortunately, the FIR filter algorithm is a compute-bound computation, and speeding up this computation can be achieved through systolic approach. Prior to designing the SA FIR filter hardware module in Quartus II, the FIR filter was first designed and analyzed via MATLAB to obtain the filter coefficients and simulation results needed in hardware design. Verification and performance analyses of the SA FIR filter were done based on both simulation results from MATLAB and hardware designs. Simulation result of the SA FIR filter proved the capability of SA architecture to produce high computational throughput, but at the expense of a large number of resources. In addition, the simulation results displayed some limitations of this particular design in terms of its response time and accuracy of the results. Thus, improvements of the design have been proposed to increase its performance.
format	Thesis
author	Kadir, Ezdiani Idayu
author_facet	Kadir, Ezdiani Idayu
author_sort	Kadir, Ezdiani Idayu
title	Systolic array architecture and its application in finite impulse response filter design
title_short	Systolic array architecture and its application in finite impulse response filter design
title_full	Systolic array architecture and its application in finite impulse response filter design
title_fullStr	Systolic array architecture and its application in finite impulse response filter design
title_full_unstemmed	Systolic array architecture and its application in finite impulse response filter design
title_sort	systolic array architecture and its application in finite impulse response filter design
publishDate	2013
url	http://eprints.utm.my/id/eprint/33298/5/EzdianiIdayuKadirMFKE2013.pdf http://eprints.utm.my/id/eprint/33298/
_version_	1643649289610592256
score	13.211869

Systolic array architecture and its application in finite impulse response filter design

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