Thermal And Flicker Noise Analysis In Sample And Hold Circuit
In low-frequency applications, noise is becoming more of an issue as the MOS size reduced. Therefore, the flicker noise and thermal noise are one of the issues found in low-frequency applications. In this work, the thermal noise and flicker noise are modelled and measured on the sample-and-hold c...
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| 第一著者: | |
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| フォーマット: | 学位論文 |
| 言語: | English |
| 出版事項: |
2015
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| 主題: | |
| オンライン･アクセス: | http://eprints.usm.my/46871/1/Thermal%20And%20Flicker%20Noise%20Analysis%20In%20Sample%20And%20Hold%20Circuit.pdf http://eprints.usm.my/46871/ |
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| 要約: | In low-frequency applications, noise is becoming more of an issue as the MOS
size reduced. Therefore, the flicker noise and thermal noise are one of the issues found
in low-frequency applications. In this work, the thermal noise and flicker noise are
modelled and measured on the sample-and-hold circuit, based on Fully Differential
Folded Cascode with Common Mode Feedback. The thermal noise analysis and flicker
noise analysis are performed by varying the capacitance value and transistor sizes in
the sample-and-hold circuit. In thermal noise analysis, the maximum output SNR
measured is -120.28dB with 0.642uV/√Hz input thermal noise and transistor size for
NMOS is set to 8μm. The maximum output SNR obtained for flicker noise is -83.27dB
for 1uA input noise with low capacitance value 0.5pF and is measured at 1Hz
frequency in sample-and-hold circuit. |
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