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Effective implementation of AES-XTS on FPGA

This paper proposes an effective FPGA implementation for data storage encryption. Throughput, area and power consumption are the most important parameters to evaluate any FPGA implemented design. Our proposed design not only achieves a high throughput but also a considerable amount of throughput/are...

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Main Authors: Ahmed, Shakil, Samsudin, Khairulmizam, Ramli, Abdul Rahman, Rokhani, Fakhrul Zaman
Format: Conference or Workshop Item
Language:English
Published: IEEE 2011
Online Access:http://psasir.upm.edu.my/id/eprint/68776/1/Effective%20implementation%20of%20AES-XTS%20on%20FPGA.pdf
http://psasir.upm.edu.my/id/eprint/68776/
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spelling my.upm.eprints.687762019-06-10T03:34:02Z http://psasir.upm.edu.my/id/eprint/68776/ Effective implementation of AES-XTS on FPGA Ahmed, Shakil Samsudin, Khairulmizam Ramli, Abdul Rahman Rokhani, Fakhrul Zaman This paper proposes an effective FPGA implementation for data storage encryption. Throughput, area and power consumption are the most important parameters to evaluate any FPGA implemented design. Our proposed design not only achieves a high throughput but also a considerable amount of throughput/area that is better compared to current implementations. The proposed implementation gives a memory based pipelined architecture. The design achieves a throughput of 5.25 Gb/sec that is relatively better than any other FPGA implementation to date. Xilinx ISE 10.1 is used as a design tool and Verilog HDL is used to code the design. IEEE 2011 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/68776/1/Effective%20implementation%20of%20AES-XTS%20on%20FPGA.pdf Ahmed, Shakil and Samsudin, Khairulmizam and Ramli, Abdul Rahman and Rokhani, Fakhrul Zaman (2011) Effective implementation of AES-XTS on FPGA. In: 2011 IEEE Region 10 Conference (TENCON 2011), 21-24 Nov. 2011, Bali, Indonesia. (pp. 184-186). 10.1109/TENCON.2011.6129088
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
language English
description This paper proposes an effective FPGA implementation for data storage encryption. Throughput, area and power consumption are the most important parameters to evaluate any FPGA implemented design. Our proposed design not only achieves a high throughput but also a considerable amount of throughput/area that is better compared to current implementations. The proposed implementation gives a memory based pipelined architecture. The design achieves a throughput of 5.25 Gb/sec that is relatively better than any other FPGA implementation to date. Xilinx ISE 10.1 is used as a design tool and Verilog HDL is used to code the design.
format Conference or Workshop Item
author Ahmed, Shakil
Samsudin, Khairulmizam
Ramli, Abdul Rahman
Rokhani, Fakhrul Zaman
spellingShingle Ahmed, Shakil
Samsudin, Khairulmizam
Ramli, Abdul Rahman
Rokhani, Fakhrul Zaman
Effective implementation of AES-XTS on FPGA
author_facet Ahmed, Shakil
Samsudin, Khairulmizam
Ramli, Abdul Rahman
Rokhani, Fakhrul Zaman
author_sort Ahmed, Shakil
title Effective implementation of AES-XTS on FPGA
title_short Effective implementation of AES-XTS on FPGA
title_full Effective implementation of AES-XTS on FPGA
title_fullStr Effective implementation of AES-XTS on FPGA
title_full_unstemmed Effective implementation of AES-XTS on FPGA
title_sort effective implementation of aes-xts on fpga
publisher IEEE
publishDate 2011
url http://psasir.upm.edu.my/id/eprint/68776/1/Effective%20implementation%20of%20AES-XTS%20on%20FPGA.pdf
http://psasir.upm.edu.my/id/eprint/68776/
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score 13.211869

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