A review on path collisions and resources usage in hybrid optical network on chip (HONoC)
System-on-chip (SoC) architectures are getting communication-bound both from physical wiring and distributed computation point of view. Wiring delays are becoming dominating over gate delays, which favors short links. The larger SoC the more probably the overall computation is heterogeneous and loca...
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| Main Authors: | , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2015
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| Online Access: | http://psasir.upm.edu.my/id/eprint/56018/1/A%20review%20on%20path%20collisions%20and%20resources%20usage%20in%20hybrid%20optical%20network%20on%20chip%20%28HONoC%29.pdf http://psasir.upm.edu.my/id/eprint/56018/ |
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