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A review on path collisions and resources usage in hybrid optical network on chip (HONoC)

System-on-chip (SoC) architectures are getting communication-bound both from physical wiring and distributed computation point of view. Wiring delays are becoming dominating over gate delays, which favors short links. The larger SoC the more probably the overall computation is heterogeneous and loca...

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Main Authors: Razali, Rina Azlin, Othman, Mohamed
Format: Conference or Workshop Item
Language:English
Published: IEEE 2015
Online Access:http://psasir.upm.edu.my/id/eprint/56018/1/A%20review%20on%20path%20collisions%20and%20resources%20usage%20in%20hybrid%20optical%20network%20on%20chip%20%28HONoC%29.pdf
http://psasir.upm.edu.my/id/eprint/56018/
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spelling my.upm.eprints.560182017-07-03T09:28:27Z http://psasir.upm.edu.my/id/eprint/56018/ A review on path collisions and resources usage in hybrid optical network on chip (HONoC) Razali, Rina Azlin Othman, Mohamed System-on-chip (SoC) architectures are getting communication-bound both from physical wiring and distributed computation point of view. Wiring delays are becoming dominating over gate delays, which favors short links. The larger SoC the more probably the overall computation is heterogeneous and localized rather than evenly balanced over the chip. These two factors motivate Network-on-Chip (NoC) that brings the techniques developed for macro-scale, multi-hop networks into a chip. But due to shrinkage of transistors and integration of billions of transistors in a single chip, has made NoC no longer suitable to cater for high latency and demand of bandwidth in a multicore processor environment. Thus they have introduce HONoC (hybrid optical network on chip) to cater for the high latency and demand in bandwidth. There are many research that focus on the area of architecture, routing algorithm and switching strategies in order to make the communication run optimally in HONoC. The purpose of this paper is to evaluate main problems in HONoC. From the evaluation, three main problems has been identified which are path collisions, low resource usage and high power consumption in HONoC. IEEE 2015 Conference or Workshop Item PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/56018/1/A%20review%20on%20path%20collisions%20and%20resources%20usage%20in%20hybrid%20optical%20network%20on%20chip%20%28HONoC%29.pdf Razali, Rina Azlin and Othman, Mohamed (2015) A review on path collisions and resources usage in hybrid optical network on chip (HONoC). In: 2015 IEEE Student Conference on Research and Development (SCOReD), 13-14 Dec. 2015, Berjaya Times Square Hotel, Kuala Lumpur, Malaysia. (pp. 162-165). 10.1109/SCORED.2015.7449316
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
language English
description System-on-chip (SoC) architectures are getting communication-bound both from physical wiring and distributed computation point of view. Wiring delays are becoming dominating over gate delays, which favors short links. The larger SoC the more probably the overall computation is heterogeneous and localized rather than evenly balanced over the chip. These two factors motivate Network-on-Chip (NoC) that brings the techniques developed for macro-scale, multi-hop networks into a chip. But due to shrinkage of transistors and integration of billions of transistors in a single chip, has made NoC no longer suitable to cater for high latency and demand of bandwidth in a multicore processor environment. Thus they have introduce HONoC (hybrid optical network on chip) to cater for the high latency and demand in bandwidth. There are many research that focus on the area of architecture, routing algorithm and switching strategies in order to make the communication run optimally in HONoC. The purpose of this paper is to evaluate main problems in HONoC. From the evaluation, three main problems has been identified which are path collisions, low resource usage and high power consumption in HONoC.
format Conference or Workshop Item
author Razali, Rina Azlin
Othman, Mohamed
spellingShingle Razali, Rina Azlin
Othman, Mohamed
A review on path collisions and resources usage in hybrid optical network on chip (HONoC)
author_facet Razali, Rina Azlin
Othman, Mohamed
author_sort Razali, Rina Azlin
title A review on path collisions and resources usage in hybrid optical network on chip (HONoC)
title_short A review on path collisions and resources usage in hybrid optical network on chip (HONoC)
title_full A review on path collisions and resources usage in hybrid optical network on chip (HONoC)
title_fullStr A review on path collisions and resources usage in hybrid optical network on chip (HONoC)
title_full_unstemmed A review on path collisions and resources usage in hybrid optical network on chip (HONoC)
title_sort review on path collisions and resources usage in hybrid optical network on chip (honoc)
publisher IEEE
publishDate 2015
url http://psasir.upm.edu.my/id/eprint/56018/1/A%20review%20on%20path%20collisions%20and%20resources%20usage%20in%20hybrid%20optical%20network%20on%20chip%20%28HONoC%29.pdf
http://psasir.upm.edu.my/id/eprint/56018/
_version_ 1643836066607661056
score 13.211869

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