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An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter

This brief introduces an improved Wilson current mirror level shifter (WCMLS) circuit designed in CMOS 55 nm technology, optimized for ultra-low voltage applications. We aim to balance speed, power, and area by employing specific architectural choices in its pull-up and pull-down networks. The pull-...

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Main Authors: Wang, Chao, Lim, Yang Wei, Ji, Yuxin, Huang, Jiajie, Lu, Wangzilu, Rokhani, Fakhrul Zaman, Ismail, Yehea, Li, Yongfu
Format: Article
Published: Institute of Electrical and Electronics Engineers 2024
Online Access:http://psasir.upm.edu.my/id/eprint/112098/
https://ieeexplore.ieee.org/document/10475672
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spelling my.upm.eprints.1120982024-10-23T07:31:21Z http://psasir.upm.edu.my/id/eprint/112098/ An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter Wang, Chao Lim, Yang Wei Ji, Yuxin Huang, Jiajie Lu, Wangzilu Rokhani, Fakhrul Zaman Ismail, Yehea Li, Yongfu This brief introduces an improved Wilson current mirror level shifter (WCMLS) circuit designed in CMOS 55 nm technology, optimized for ultra-low voltage applications. We aim to balance speed, power, and area by employing specific architectural choices in its pull-up and pull-down networks. The pull-up network (PUN) employs a Wilson current mirror to effectively reduce static current. The pull-down network (PDN) incorporates a diode-connected P-type transistor as a current limiter, further reducing static power consumption. An improved split-controlled inverter is introduced as the output driver to further minimize both static and short-circuit currents. The proposed level shifter can operate at a minimum $V_{DDL}$ of 100 mV at $V_{DDH}=$ 1.2 V and 1 MHz input frequency. Performance comparison with prior works reveals a significant performance improvement in terms of delay, power-delay product (PDP), and energy-delay product (EDP), with a delay of 4.79 ns, a PDP of 355 ns*nW, and an EDP of 326 fJ*ns when operating in a conversion range of 0.3 - 1.2 V, making it a robust choice for energy-efficient ultra-low voltage level shifting applications. Institute of Electrical and Electronics Engineers 2024 Article PeerReviewed Wang, Chao and Lim, Yang Wei and Ji, Yuxin and Huang, Jiajie and Lu, Wangzilu and Rokhani, Fakhrul Zaman and Ismail, Yehea and Li, Yongfu (2024) An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter. IEEE Transactions on Circuits and Systems II: Express Briefs, 71 (5). pp. 2569-2573. ISSN 1549-7747; ESSN: 1558-3791 https://ieeexplore.ieee.org/document/10475672 10.1109/TCSII.2024.3379448
institution Universiti Putra Malaysia
building UPM Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Putra Malaysia
content_source UPM Institutional Repository
url_provider http://psasir.upm.edu.my/
description This brief introduces an improved Wilson current mirror level shifter (WCMLS) circuit designed in CMOS 55 nm technology, optimized for ultra-low voltage applications. We aim to balance speed, power, and area by employing specific architectural choices in its pull-up and pull-down networks. The pull-up network (PUN) employs a Wilson current mirror to effectively reduce static current. The pull-down network (PDN) incorporates a diode-connected P-type transistor as a current limiter, further reducing static power consumption. An improved split-controlled inverter is introduced as the output driver to further minimize both static and short-circuit currents. The proposed level shifter can operate at a minimum $V_{DDL}$ of 100 mV at $V_{DDH}=$ 1.2 V and 1 MHz input frequency. Performance comparison with prior works reveals a significant performance improvement in terms of delay, power-delay product (PDP), and energy-delay product (EDP), with a delay of 4.79 ns, a PDP of 355 ns*nW, and an EDP of 326 fJ*ns when operating in a conversion range of 0.3 - 1.2 V, making it a robust choice for energy-efficient ultra-low voltage level shifting applications.
format Article
author Wang, Chao
Lim, Yang Wei
Ji, Yuxin
Huang, Jiajie
Lu, Wangzilu
Rokhani, Fakhrul Zaman
Ismail, Yehea
Li, Yongfu
spellingShingle Wang, Chao
Lim, Yang Wei
Ji, Yuxin
Huang, Jiajie
Lu, Wangzilu
Rokhani, Fakhrul Zaman
Ismail, Yehea
Li, Yongfu
An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter
author_facet Wang, Chao
Lim, Yang Wei
Ji, Yuxin
Huang, Jiajie
Lu, Wangzilu
Rokhani, Fakhrul Zaman
Ismail, Yehea
Li, Yongfu
author_sort Wang, Chao
title An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter
title_short An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter
title_full An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter
title_fullStr An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter
title_full_unstemmed An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter
title_sort ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter
publisher Institute of Electrical and Electronics Engineers
publishDate 2024
url http://psasir.upm.edu.my/id/eprint/112098/
https://ieeexplore.ieee.org/document/10475672
_version_ 1814054744737447936
score 13.211869

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