An ultra low voltage energy efficient level shifter with current limiter and improved split-controlled inverter
This brief introduces an improved Wilson current mirror level shifter (WCMLS) circuit designed in CMOS 55 nm technology, optimized for ultra-low voltage applications. We aim to balance speed, power, and area by employing specific architectural choices in its pull-up and pull-down networks. The pull-...
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| Main Authors: | , , , , , , , |
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| Format: | Article |
| Published: |
Institute of Electrical and Electronics Engineers
2024
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| Online Access: | http://psasir.upm.edu.my/id/eprint/112098/ https://ieeexplore.ieee.org/document/10475672 |
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| Summary: | This brief introduces an improved Wilson current mirror level shifter (WCMLS) circuit designed in CMOS 55 nm technology, optimized for ultra-low voltage applications. We aim to balance speed, power, and area by employing specific architectural choices in its pull-up and pull-down networks. The pull-up network (PUN) employs a Wilson current mirror to effectively reduce static current. The pull-down network (PDN) incorporates a diode-connected P-type transistor as a current limiter, further reducing static power consumption. An improved split-controlled inverter is introduced as the output driver to further minimize both static and short-circuit currents. The proposed level shifter can operate at a minimum $V_{DDL}$ of 100 mV at $V_{DDH}=$ 1.2 V and 1 MHz input frequency. Performance comparison with prior works reveals a significant performance improvement in terms of delay, power-delay product (PDP), and energy-delay product (EDP), with a delay of 4.79 ns, a PDP of 355 ns*nW, and an EDP of 326 fJ*ns when operating in a conversion range of 0.3 - 1.2 V, making it a robust choice for energy-efficient ultra-low voltage level shifting applications. |
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