Improved series resistance model for CMOS ESD diodes
Compact diode models normally available in commercial simulators like Spectre or HSPICE do not scale the series resistance with P-N distance. The standard diode models scale with drawn area, assuming the current is vertical. However the diodes used for ESD protection in CMOS are operating as lateral...
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2017
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| Online Access: | http://dspace.uniten.edu.my:8080/jspui/handle/123456789/5263 |
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| Summary: | Compact diode models normally available in commercial simulators like Spectre or HSPICE do not scale the series resistance with P-N distance. The standard diode models scale with drawn area, assuming the current is vertical. However the diodes used for ESD protection in CMOS are operating as lateral diodes, so the resistance should scale with width, not area. This is a serious problem for circuit designers. Accurate series resistance in the diode forward region is critical especially for designing ESD protection circuits. This paper analyzes the effect of diode width and P to N (P active to N-tap active) distance on the extracted model Rs value in the standard level 3 SPICE diode model. Diodes of various widths and P-N distance were designed and fabricated in a CMOS 130 nm technology to get actual data measurements. Parameter extraction was done using the commercial BSIMProPlus model extraction software. Different diode widths and P-N distances produce forward IV curves with different slope, due to the changing series resistance. The slope represents the incremental series resistance. This study has been done with two types of diode, PN diode (P active in Nwell diode) and NP diode (N active in Pwell diode). The extracted Rs value shows a linear relationship to P-N distance and is proportional to inverse drawn width. © 2008 IEEE. |
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