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LFSR based fast seed selection technique reducing test time of I DDQ testing

This paper proposed IDDQ testing of combinational circuit using Linear Feedback Shift Register (LFSR) based fast seed selection technique. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing. To reduce test t...

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Main Authors:	Islam S.Z., Jidin R.B., Ali M.A.M.
Other Authors:	55432804400
Format:	Conference paper
Published:	2023
Subjects:	Bridging fault I<sub>DDQ</sub> LFSR Combinatorial circuits Industrial electronics Shift registers Benchmark circuit Bit flipping CMOS circuits Combinational circuits IDDQ testing Linear feedback shift registers Logic testing Seed selection Switching activities Test time Testing time Delay circuits
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id	my.uniten.dspace-30737
record_format	dspace
spelling	my.uniten.dspace-307372023-12-29T15:52:10Z LFSR based fast seed selection technique reducing test time of I DDQ testing Islam S.Z. Jidin R.B. Ali M.A.M. 55432804400 6508169028 6507416666 Bridging fault I<sub>DDQ</sub> LFSR Combinatorial circuits Industrial electronics Shift registers Benchmark circuit Bit flipping Bridging fault CMOS circuits Combinational circuits IDDQ testing Linear feedback shift registers Logic testing Seed selection Switching activities Test time Testing time Delay circuits This paper proposed IDDQ testing of combinational circuit using Linear Feedback Shift Register (LFSR) based fast seed selection technique. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing. To reduce test time of IDDQ testing, bit-flipping technique is integrated with LFSR to reduce lower to higher (L to H) switching activities for combinational circuits. Experimental results for ISCAS'85 and ISCAS'89 benchmark circuits show the effectiveness (7% improvement) of the technique for reducing testing time delay. � 2009 IEEE. Final 2023-12-29T07:52:10Z 2023-12-29T07:52:10Z 2009 Conference paper 10.1109/ISIEA.2009.5356430 2-s2.0-76449108054 https://www.scopus.com/inward/record.uri?eid=2-s2.0-76449108054&doi=10.1109%2fISIEA.2009.5356430&partnerID=40&md5=71631f52a949de98a4dcd45dc30c57da https://irepository.uniten.edu.my/handle/123456789/30737 1 5356430 362 364 Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
topic	Bridging fault I<sub>DDQ</sub> LFSR Combinatorial circuits Industrial electronics Shift registers Benchmark circuit Bit flipping Bridging fault CMOS circuits Combinational circuits IDDQ testing Linear feedback shift registers Logic testing Seed selection Switching activities Test time Testing time Delay circuits
spellingShingle	Bridging fault I<sub>DDQ</sub> LFSR Combinatorial circuits Industrial electronics Shift registers Benchmark circuit Bit flipping Bridging fault CMOS circuits Combinational circuits IDDQ testing Linear feedback shift registers Logic testing Seed selection Switching activities Test time Testing time Delay circuits Islam S.Z. Jidin R.B. Ali M.A.M. LFSR based fast seed selection technique reducing test time of I DDQ testing
description	This paper proposed IDDQ testing of combinational circuit using Linear Feedback Shift Register (LFSR) based fast seed selection technique. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing. To reduce test time of IDDQ testing, bit-flipping technique is integrated with LFSR to reduce lower to higher (L to H) switching activities for combinational circuits. Experimental results for ISCAS'85 and ISCAS'89 benchmark circuits show the effectiveness (7% improvement) of the technique for reducing testing time delay. � 2009 IEEE.
author2	55432804400
author_facet	55432804400 Islam S.Z. Jidin R.B. Ali M.A.M.
format	Conference paper
author	Islam S.Z. Jidin R.B. Ali M.A.M.
author_sort	Islam S.Z.
title	LFSR based fast seed selection technique reducing test time of I DDQ testing
title_short	LFSR based fast seed selection technique reducing test time of I DDQ testing
title_full	LFSR based fast seed selection technique reducing test time of I DDQ testing
title_fullStr	LFSR based fast seed selection technique reducing test time of I DDQ testing
title_full_unstemmed	LFSR based fast seed selection technique reducing test time of I DDQ testing
title_sort	lfsr based fast seed selection technique reducing test time of i ddq testing
publishDate	2023
_version_	1806423433016246272
score	13.222552

LFSR based fast seed selection technique reducing test time of I DDQ testing

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