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FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection

Currently, FPGA (Field Programmable Gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall i...

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書誌詳細
主要な著者:	Emilliano, Chakrabarty C.K., Basri A., Ramasamy A.K., Ping L.C.
その他の著者:	35974769600
フォーマット:	論文
出版事項:	2023
主題:	ADC with peak detector block Counter with reset block FPGA simulation FPGA technology Partial discharge detection Real time processing Underground cable VHDL programming
タグ:	タグ追加タグなし, このレコードへの初めてのタグを付けませんか!

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