所蔵: VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 10.1i (Xilinx) and ISE Xilinx Synthesized Technology (XST) using Very high integrated circuit Hardware Description Language...

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主要な著者:	Emilliano, Chakrabarty C.K., Ghani A.B.A., Ramasamy A.K.
その他の著者:	35974769600
フォーマット:	Conference paper
出版事項:	2023
主題:	ADC with peak detector block Counter with reset block FPGA simulation FPGA technology Partial discharge detection Real time processing Underground cable VHDL programming Cables Computer hardware description languages Field programmable gate arrays (FPGA) Partial discharges Research Signal detection Technology Underground cables Peak detectors Realtime processing Detectors
タグ:	タグ追加タグなし, このレコードへの初めてのタグを付けませんか!

VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA

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