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FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection

Currently, FPGA (Field Programmable Gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall i...

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Main Authors:	Emilliano, Chakrabarty C.K., Basri A., Ramasamy A.K., Ping L.C.
Other Authors:	35974769600
Format:	Article
Published:	2023
Subjects:	ADC with peak detector block Counter with reset block FPGA simulation FPGA technology Partial discharge detection Real time processing Underground cable VHDL programming
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id	my.uniten.dspace-30681
record_format	dspace
spelling	my.uniten.dspace-306812023-12-29T15:51:18Z FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection Emilliano Chakrabarty C.K. Basri A. Ramasamy A.K. Ping L.C. 35974769600 6701755282 37058575100 16023154400 36024204500 ADC with peak detector block Counter with reset block FPGA simulation FPGA technology Partial discharge detection Real time processing Underground cable VHDL programming Currently, FPGA (Field Programmable Gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 9.2i (Xilinx) and Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. Final 2023-12-29T07:51:18Z 2023-12-29T07:51:18Z 2010 Article 2-s2.0-84865150970 https://www.scopus.com/inward/record.uri?eid=2-s2.0-84865150970&partnerID=40&md5=cf6d3e78604baa7f697b14522211289c https://irepository.uniten.edu.my/handle/123456789/30681 2 1 29 37 Scopus
institution	Universiti Tenaga Nasional
building	UNITEN Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Tenaga Nasional
content_source	UNITEN Institutional Repository
url_provider	http://dspace.uniten.edu.my/
topic	ADC with peak detector block Counter with reset block FPGA simulation FPGA technology Partial discharge detection Real time processing Underground cable VHDL programming
spellingShingle	ADC with peak detector block Counter with reset block FPGA simulation FPGA technology Partial discharge detection Real time processing Underground cable VHDL programming Emilliano Chakrabarty C.K. Basri A. Ramasamy A.K. Ping L.C. FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection
description	Currently, FPGA (Field Programmable Gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 9.2i (Xilinx) and Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of Field Programming Gate Array (FPGA) for the detection and counting of partial discharge signals in underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns.
author2	35974769600
author_facet	35974769600 Emilliano Chakrabarty C.K. Basri A. Ramasamy A.K. Ping L.C.
format	Article
author	Emilliano Chakrabarty C.K. Basri A. Ramasamy A.K. Ping L.C.
author_sort	Emilliano
title	FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection
title_short	FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection
title_full	FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection
title_fullStr	FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection
title_full_unstemmed	FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection
title_sort	fpga simulation of ad converter by using giga hertz speed data acquisition for partial discharge detection
publishDate	2023
_version_	1806428245703262208
score	13.211869

FPGA simulation of AD converter by using Giga Hertz speed data acquisition for partial discharge detection

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