Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device
In this paper, the effect of high permittivity gate spacer on short channel effects (SCEs) for the 16 nm double-gate finFET is investigated, with the output responses optimized using L9 orthogonal array (OA) Taguchi method. The determination is done through Signal-to-noise ratio to the effectiveness...
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my.uniten.dspace-272482023-05-29T17:41:34Z Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device Roslan A.F. Salehuddin F. Zain A.S.M. Kaharudin K.E. Mohamad N.R. Maheran A.H.A. Haroon H. Razak H.A. Idris S.K. Ahmad I. 57203514087 36239165300 55925762500 56472706900 55383652800 36570222300 35108985200 57222550982 57202632295 12792216600 In this paper, the effect of high permittivity gate spacer on short channel effects (SCEs) for the 16 nm double-gate finFET is investigated, with the output responses optimized using L9 orthogonal array (OA) Taguchi method. The determination is done through Signal-to-noise ratio to the effectiveness of the process parameters towards four output responses such as threshold voltage (VTH), drive current (ION), leakage current (IOFF) and Subthreshold Swing (SS). The virtual fabrication of the 16 nm double-gate fin FET was performed using ANTHENA module while the electrical characteristics of the device were simulated using ATLAS module. These two modules were combined with Taguchi method to aid in designing and optimizing the process parameters. The electrical characterization was performed and significant improvement could be seen on the TiO2 and HfO2 material in terms of the ION/IOFF ratio obtained at 4.03x106 and 3.61x106 respectively for 0.179�12.7% V of VTH. It can be observed that when approaching a higher value of dielectric constant (high-K), the ION increases while the SS and IOFF decreases. As conclusion, the output responses from high-K materials have been proven to meet the minimum requirement by International Technology Roadmap Semiconductor (ITRS) 2013 for high performance Multi-Gate technology for the year 2015. � 2022 College of Engineering, Universiti Teknologi MARA (UiTM), Malaysia. Final 2023-05-29T09:41:33Z 2023-05-29T09:41:33Z 2022 Article 2-s2.0-85125867494 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85125867494&partnerID=40&md5=d5902ba225b0985179efce6a9cb20946 https://irepository.uniten.edu.my/handle/123456789/27248 19 1 145 162 UiTM Press Scopus |
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In this paper, the effect of high permittivity gate spacer on short channel effects (SCEs) for the 16 nm double-gate finFET is investigated, with the output responses optimized using L9 orthogonal array (OA) Taguchi method. The determination is done through Signal-to-noise ratio to the effectiveness of the process parameters towards four output responses such as threshold voltage (VTH), drive current (ION), leakage current (IOFF) and Subthreshold Swing (SS). The virtual fabrication of the 16 nm double-gate fin FET was performed using ANTHENA module while the electrical characteristics of the device were simulated using ATLAS module. These two modules were combined with Taguchi method to aid in designing and optimizing the process parameters. The electrical characterization was performed and significant improvement could be seen on the TiO2 and HfO2 material in terms of the ION/IOFF ratio obtained at 4.03x106 and 3.61x106 respectively for 0.179�12.7% V of VTH. It can be observed that when approaching a higher value of dielectric constant (high-K), the ION increases while the SS and IOFF decreases. As conclusion, the output responses from high-K materials have been proven to meet the minimum requirement by International Technology Roadmap Semiconductor (ITRS) 2013 for high performance Multi-Gate technology for the year 2015. � 2022 College of Engineering, Universiti Teknologi MARA (UiTM), Malaysia. |
| author2 |
57203514087 |
| author_facet |
57203514087 Roslan A.F. Salehuddin F. Zain A.S.M. Kaharudin K.E. Mohamad N.R. Maheran A.H.A. Haroon H. Razak H.A. Idris S.K. Ahmad I. |
| format |
Article |
| author |
Roslan A.F. Salehuddin F. Zain A.S.M. Kaharudin K.E. Mohamad N.R. Maheran A.H.A. Haroon H. Razak H.A. Idris S.K. Ahmad I. |
| spellingShingle |
Roslan A.F. Salehuddin F. Zain A.S.M. Kaharudin K.E. Mohamad N.R. Maheran A.H.A. Haroon H. Razak H.A. Idris S.K. Ahmad I. Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device |
| author_sort |
Roslan A.F. |
| title |
Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device |
| title_short |
Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device |
| title_full |
Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device |
| title_fullStr |
Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device |
| title_full_unstemmed |
Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device |
| title_sort |
statistical optimization influence on high permittivity gate spacer in 16nm dg-finfet device |
| publisher |
UiTM Press |
| publishDate |
2023 |
| _version_ |
1806426382548336640 |
| score |
13.211869 |