Performance Optimization in Network-on-Chip (NoC) Architecture
The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing th...
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LAP LAMBERT Academic Publishing
2014
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Online Access: | http://ir.unimas.my/id/eprint/41657/1/nurbaizura.pdf http://ir.unimas.my/id/eprint/41657/ |
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my.unimas.ir.416572023-04-12T02:25:18Z http://ir.unimas.my/id/eprint/41657/ Performance Optimization in Network-on-Chip (NoC) Architecture Nurbaizura, Ramji Asrani, Lit QA75 Electronic computers. Computer science The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing the topological structure of the on-chip network which fulfilled the application requirements. Therefore, Network Partitioning technique is proposed to obtain the optimal design of networks based on its performance. The performance of NoC is measured through several metrics namely average queue size, waiting time and packet loss. To validate the efficiency, this technique is applied in a case study of MPEG-4 video application. It is expected that the proposed technique is an optimistic way in enhancing the performance of NoC compared to other well known techniques. LAP LAMBERT Academic Publishing 2014-02-23 Book PeerReviewed text en http://ir.unimas.my/id/eprint/41657/1/nurbaizura.pdf Nurbaizura, Ramji and Asrani, Lit (2014) Performance Optimization in Network-on-Chip (NoC) Architecture. LAP LAMBERT Academic Publishing. ISBN 978-3-659-52335-9 |
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QA75 Electronic computers. Computer science Nurbaizura, Ramji Asrani, Lit Performance Optimization in Network-on-Chip (NoC) Architecture |
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The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing the topological structure of the on-chip network which fulfilled the application requirements. Therefore, Network Partitioning technique is proposed to obtain the optimal design of networks based on its performance. The performance of NoC is measured through several metrics namely average queue size, waiting time and packet loss. To validate the efficiency, this technique is applied in a case study of MPEG-4 video application. It is expected that the proposed technique is an optimistic way in enhancing the performance of NoC compared to other well known techniques. |
format |
Book |
author |
Nurbaizura, Ramji Asrani, Lit |
author_facet |
Nurbaizura, Ramji Asrani, Lit |
author_sort |
Nurbaizura, Ramji |
title |
Performance Optimization in Network-on-Chip (NoC) Architecture |
title_short |
Performance Optimization in Network-on-Chip (NoC) Architecture |
title_full |
Performance Optimization in Network-on-Chip (NoC) Architecture |
title_fullStr |
Performance Optimization in Network-on-Chip (NoC) Architecture |
title_full_unstemmed |
Performance Optimization in Network-on-Chip (NoC) Architecture |
title_sort |
performance optimization in network-on-chip (noc) architecture |
publisher |
LAP LAMBERT Academic Publishing |
publishDate |
2014 |
url |
http://ir.unimas.my/id/eprint/41657/1/nurbaizura.pdf http://ir.unimas.my/id/eprint/41657/ |
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1762965693100195840 |
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13.211869 |