Performance Optimization in Network-on-Chip (NoC) Architecture
The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing th...
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| 主要な著者: | , |
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| フォーマット: | 図書 |
| 言語: | English |
| 出版事項: |
LAP LAMBERT Academic Publishing
2014
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| 主題: | |
| オンライン･アクセス: | http://ir.unimas.my/id/eprint/41657/1/nurbaizura.pdf http://ir.unimas.my/id/eprint/41657/ |
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| 要約: | The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing the topological structure of the on-chip network which fulfilled the application requirements. Therefore, Network Partitioning technique is proposed to obtain the optimal design of networks based on its performance. The performance of NoC is measured through several metrics namely average queue size, waiting time and packet loss. To validate the efficiency, this technique is applied in a case study of MPEG-4 video application. It is expected that the proposed technique is an optimistic way in enhancing the performance of NoC compared to other well known techniques. |
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