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Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications

A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area als...

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Main Author:	Mohd Nazri Md Rejab
Other Authors:	Nazuhusna Khalid (Advisor)
Format:	Learning Object
Language:	English
Published:	Universiti Malaysia Perlis 2008
Subjects:	Multipliers Multipliers (Mathematical analysis) High-speed multiplier Metal oxide semiconductors, Complementary Multiplier accumulator (MAC) Very Large Scale Integration (VLSI)
Online Access:	http://dspace.unimap.edu.my/xmlui/handle/123456789/2012
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id	my.unimap-2012
record_format	dspace
spelling	my.unimap-20122008-09-09T06:55:57Z Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications Mohd Nazri Md Rejab Nazuhusna Khalid (Advisor) Multipliers Multipliers (Mathematical analysis) High-speed multiplier Metal oxide semiconductors, Complementary Multiplier accumulator (MAC) Very Large Scale Integration (VLSI) A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area. The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plans are to instantiate a good design and modify it for low power and speed and prepare its layout using TSMC 0.18um in Mentor Graphic. I have used a unique technique for power reduction in Wallace tree. The design also proposed a method to calculate 2’s complement of multiplicand for final Partial Product if using MBE technique. This method has been used in the design for speed enhancement and power reduction. The total designed of MAC unit consumed about 15.3438nW and power delay product is approximately 0.056fJ. Hence, it proven that this MAC unit design had saved power consumption and has also a very high speed performance with 273.97MHz. 2008-09-09T06:55:57Z 2008-09-09T06:55:57Z 2008-04 Learning Object http://hdl.handle.net/123456789/2012 en Universiti Malaysia Perlis School of Microelectronic Engineering
institution	Universiti Malaysia Perlis
building	UniMAP Library
collection	Institutional Repository
continent	Asia
country	Malaysia
content_provider	Universiti Malaysia Perlis
content_source	UniMAP Library Digital Repository
url_provider	http://dspace.unimap.edu.my/
language	English
topic	Multipliers Multipliers (Mathematical analysis) High-speed multiplier Metal oxide semiconductors, Complementary Multiplier accumulator (MAC) Very Large Scale Integration (VLSI)
spellingShingle	Multipliers Multipliers (Mathematical analysis) High-speed multiplier Metal oxide semiconductors, Complementary Multiplier accumulator (MAC) Very Large Scale Integration (VLSI) Mohd Nazri Md Rejab Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications
description	A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area. The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plans are to instantiate a good design and modify it for low power and speed and prepare its layout using TSMC 0.18um in Mentor Graphic. I have used a unique technique for power reduction in Wallace tree. The design also proposed a method to calculate 2’s complement of multiplicand for final Partial Product if using MBE technique. This method has been used in the design for speed enhancement and power reduction. The total designed of MAC unit consumed about 15.3438nW and power delay product is approximately 0.056fJ. Hence, it proven that this MAC unit design had saved power consumption and has also a very high speed performance with 273.97MHz.
author2	Nazuhusna Khalid (Advisor)
author_facet	Nazuhusna Khalid (Advisor) Mohd Nazri Md Rejab
format	Learning Object
author	Mohd Nazri Md Rejab
author_sort	Mohd Nazri Md Rejab
title	Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications
title_short	Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications
title_full	Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications
title_fullStr	Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications
title_full_unstemmed	Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications
title_sort	design and realization of a high speed multiplier accumulator (mac) unit for low power applications
publisher	Universiti Malaysia Perlis
publishDate	2008
url	http://dspace.unimap.edu.my/xmlui/handle/123456789/2012
_version_	1643787530203561984
score	13.222552

Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications

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