8-bits X 8-bits modified Booth 1’s complement multiplier
With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier, thus making them suitable for various high speed...
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Universiti Malaysia Perlis
2008
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my.unimap-19342008-09-03T09:06:01Z 8-bits X 8-bits modified Booth 1’s complement multiplier Norafiza Salehan Norina Idris (Advisor) Altera Quartus II Multipliers Very Large Scale Integration (VLSI) Carry Save Adder (CSA) Multipliers (Mathematical analysis) With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier, thus making them suitable for various high speed, low power, and compact VLSI implementation. This project focuses on speed performance of the Modified Baugh-Wooley Two’s Complement Signed Multiplier. Three methods to improve speed performance of the multiplier – reduce the number of partial products and accelerate the accumulation have been discussed in literature view. For Modified Baugh-Wooley Two’s Complement Signed Multiplier the speed is improved by reducing the partial products and then summing these partial products using Carry Save Adder. The schematic design as well as speed performance analysis of this multiplier is done using Altera’s Quartus II Software and speed obtained on EPF10K70. 2008-09-03T09:06:01Z 2008-09-03T09:06:01Z 2007-05 Learning Object http://hdl.handle.net/123456789/1934 en Universiti Malaysia Perlis School of Microelectronic Engineering |
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English |
| topic |
Altera Quartus II Multipliers Very Large Scale Integration (VLSI) Carry Save Adder (CSA) Multipliers (Mathematical analysis) |
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Altera Quartus II Multipliers Very Large Scale Integration (VLSI) Carry Save Adder (CSA) Multipliers (Mathematical analysis) Norafiza Salehan 8-bits X 8-bits modified Booth 1’s complement multiplier |
| description |
With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier, thus making them suitable for various high speed, low power, and compact VLSI implementation. This project focuses on speed performance of the Modified Baugh-Wooley Two’s Complement Signed Multiplier. Three methods to improve speed performance of the multiplier – reduce the number of partial products and accelerate the accumulation have been discussed in literature view. For Modified Baugh-Wooley Two’s Complement Signed Multiplier the speed is improved by reducing the partial products and then summing these partial products using Carry Save Adder. The schematic design as well as speed performance analysis of this multiplier is done using Altera’s Quartus II Software and speed obtained on EPF10K70. |
| author2 |
Norina Idris (Advisor) |
| author_facet |
Norina Idris (Advisor) Norafiza Salehan |
| format |
Learning Object |
| author |
Norafiza Salehan |
| author_sort |
Norafiza Salehan |
| title |
8-bits X 8-bits modified Booth 1’s complement multiplier |
| title_short |
8-bits X 8-bits modified Booth 1’s complement multiplier |
| title_full |
8-bits X 8-bits modified Booth 1’s complement multiplier |
| title_fullStr |
8-bits X 8-bits modified Booth 1’s complement multiplier |
| title_full_unstemmed |
8-bits X 8-bits modified Booth 1’s complement multiplier |
| title_sort |
8-bits x 8-bits modified booth 1’s complement multiplier |
| publisher |
Universiti Malaysia Perlis |
| publishDate |
2008 |
| url |
http://dspace.unimap.edu.my/xmlui/handle/123456789/1934 |
| _version_ |
1643787491375841280 |
| score |
13.222552 |