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Diameter Optimization of Nano-scale SiNWT Based SRAM Cell

This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (N...

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Main Authors: Naif, Yasir Hashim, Hadi, Manap
Format: Conference or Workshop Item
Language:English
Published: 2015
Subjects:
QC Physics
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://umpir.ump.edu.my/id/eprint/11635/1/ICCSCE2015%20Paper.pdf
http://umpir.ump.edu.my/id/eprint/11635/
http://iccsce.acscrg.com/
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spelling my.ump.umpir.116352018-02-07T06:31:10Z http://umpir.ump.edu.my/id/eprint/11635/ Diameter Optimization of Nano-scale SiNWT Based SRAM Cell Naif, Yasir Hashim Hadi, Manap QC Physics TK Electrical engineering. Electronics Nuclear engineering This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both diameters of nanowires and logic voltage level (Vdd). And increasing of logic voltage level from 1V to 3V tends to decrease in optimized nanowires diameters but with increasing in current and power dissipation. SRAM using nanowires transistors must use logic level (2V or 2.5V) to produce SRAM with lower diameters and suitable inflection currents and then with lower power dissipation as possible. 2015-11 Conference or Workshop Item PeerReviewed application/pdf en http://umpir.ump.edu.my/id/eprint/11635/1/ICCSCE2015%20Paper.pdf Naif, Yasir Hashim and Hadi, Manap (2015) Diameter Optimization of Nano-scale SiNWT Based SRAM Cell. In: 2015 IEEE International Conference on Control System, Computing and Engineering, 27 - 29 November 2015 , Penang, Malaysia. pp. 87-90.. http://iccsce.acscrg.com/
institution Universiti Malaysia Pahang
building UMP Library
collection Institutional Repository
continent Asia
country Malaysia
content_provider Universiti Malaysia Pahang
content_source UMP Institutional Repository
url_provider http://umpir.ump.edu.my/
language English
topic QC Physics
TK Electrical engineering. Electronics Nuclear engineering
spellingShingle QC Physics
TK Electrical engineering. Electronics Nuclear engineering
Naif, Yasir Hashim
Hadi, Manap
Diameter Optimization of Nano-scale SiNWT Based SRAM Cell
description This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both diameters of nanowires and logic voltage level (Vdd). And increasing of logic voltage level from 1V to 3V tends to decrease in optimized nanowires diameters but with increasing in current and power dissipation. SRAM using nanowires transistors must use logic level (2V or 2.5V) to produce SRAM with lower diameters and suitable inflection currents and then with lower power dissipation as possible.
format Conference or Workshop Item
author Naif, Yasir Hashim
Hadi, Manap
author_facet Naif, Yasir Hashim
Hadi, Manap
author_sort Naif, Yasir Hashim
title Diameter Optimization of Nano-scale SiNWT Based SRAM Cell
title_short Diameter Optimization of Nano-scale SiNWT Based SRAM Cell
title_full Diameter Optimization of Nano-scale SiNWT Based SRAM Cell
title_fullStr Diameter Optimization of Nano-scale SiNWT Based SRAM Cell
title_full_unstemmed Diameter Optimization of Nano-scale SiNWT Based SRAM Cell
title_sort diameter optimization of nano-scale sinwt based sram cell
publishDate 2015
url http://umpir.ump.edu.my/id/eprint/11635/1/ICCSCE2015%20Paper.pdf
http://umpir.ump.edu.my/id/eprint/11635/
http://iccsce.acscrg.com/
_version_ 1643666716397404160
score 13.211869

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