Optimization of Channel Length Nano-Scale SiNWT Based SRAM Cell
This paper represents a channel length ratio optimization at a different high logic level voltage for 6-Silicon Nanowire Transistors (SiNWT) SRAM cell. This study is the first to demonstrate an optimized length ratio of nanowires with different Vdd of nano-scale SiNWT based SRAM cell. Noise margins...
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
American Institute of Physics (AIP)
2016
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| Online Access: | http://umpir.ump.edu.my/id/eprint/15319/1/1.4965107.pdf_expires%3D1479185924%26id%3Did%26accname%3Dguest%26checksum%3DB61DB192446CC5D114088756A852C2F6 http://umpir.ump.edu.my/id/eprint/15319/ http://dx.doi.org/10.1063/1.4965107 |
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